This invention relates to a process for producing a semiconductor device, more particularly to a process for forming a multilevel interconnection.
A process for forming a multilevel interconnection in the conventional process for forming a semiconductor device will be described referring to FIG. 1.
A first Al wiring 3A is first formed on the semiconductor substrate 1A, and then a first insulator film (CVD-SiO.sub.2 film) 14, a spin-on glass (SOG) film 5A and a second insulator film 16 are formed successively to form as a whole a three-layered structure insulator film. Subsequently, after via holes are formed at predetermined positions, a second Al wiring 8A is formed. Thus, a semiconductor device having a double level Al interconnection structure is completed. Such process is disclosed, for example, in Japanese Unexamined Patent Publication No. 100748/1982.
However, the conventional process for forming multilevel interconnection described above involves the following problems.
First, in the formation of the oxide film by chemical vapor deposition, a high film-forming temperature of 300.degree. C. or more is needed, so that cracking is liable to occur in the film thus formed due to thermal stress. Meanwhile, voids are liable to be formed in the Al wirings by the stress and thus the interconnections are easily disconnected when charged. Further, since a heat treatment at 300.degree. C. or more is required when the SOG film is formed, the insulator films are liable to be cracked due to the tensile stress caused by the volume shrinkage of the SOG film and voids are liable to be formed in the Al wirings due to the thermal stress increasing during the heat treatment and the like. Accordingly, not only the yield of the semiconductor devices but also reliability thereof are degraded, disadvantageously.